• Eight Input Clocks
• Differential or CMOS/TTL Format
• Any Frequency from 2kHz to 750MHz
• Fractional Scaling for 64B/66B and FEC Scaling (e.g.,64/66, 237/255, 238/255) or Any Other Downscaling Requirement
• Continuous Input Clock Quality Monitoring
• Two High-Performance DPLLs
• Hitless Reference Switching on Loss of Input
• Automatic or Manual Phase Build-Out
• Holdover on Loss of All Inputs
• Programmable Bandwidth, 0.5mHz to 400Hz
• Seven Digital Frequency Synthesizers
• Each Can Slave to Either DPLL
• Produce Any 2kHz Multiple Up to 77.76MHz
• Three Output APLLs
• Output Frequencies to 750MHz
• High Resolution Fractional Scaling for FEC and 64B/66B (e.g., 255/237, 255/238, 66/64) or Any Other Scaling Requirement
• Less than 1ps RMS Output Jitter
• Simultaneously Produce Three Low-Jitter Rates from the Same Reference (e.g., 622.08MHz for SONET, 255/237*622.08MHz for OTU2, and 156.25MHz for10GE)
• 14 Output Clocks in Seven Groups
• Nearly Any Frequency from < 1Hz to 750MHz
• Each Group Slaves to a DFS Clock, Any APLL Clock, or Any Input Clock (Divided and Scaled)
• Each Has a Differential Output (3 CML, 4 LVDS/ LVPECL) and Separate CMOS/TTL Output
• 32-Bit Frequency Divider Per Output
• IEEE 1588 Clock Features
• Steerable by Software with 2-8ns Time Resolution and 2-32ns Frequency Resolution
• 4ns Input Timestamp Accuracy and Output Edge Placement Accuracy
• Programmable Clock and Time-Alignment I/O to Synchronize All 1588 Devices in Large Systems
• Supports 1588 OC, BC, and TC Architectures
• General Features
• Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU
• Accepts and Produces Nearly Any Frequency from 1Hz Up to 750MHz
• Internal Compensation for Local Oscillator Frequency Error
• SPI™ Processor Interface
• 1.8V Operation with 3.3V I/O (5V Tolerant)
