• Three Input Clocks
• Differential or CMOS/TTL Format
• Any Frequency from 2kHz to 750MHz
• Fractional Scaling for 64B/66B and FEC Scaling (e.g., 64/66, 237/255, 238/255) or Any Other Downscaling Requirement
• Continuous Input Clock Quality Monitoring
• Automatic or Manual Clock Selection
• Three 2/4/8kHz Frame Sync Inputs
• High-Performance DPLL
• Hitless Reference Switching on Loss of Input
• Automatic or Manual Phase Build-Out
• Holdover on Loss of All Inputs
• Programmable Bandwidth, 0.5mHz to 400Hz
• Two Digital Frequency Synthesizers
• Produce Any 2kHz Multiple Up to 77.76MHz
• Per-DFS Clock Phase Adjust
• High-Performance Output APLL
• Output Frequencies to 750MHz
• High Resolution Fractional Scaling for FEC and 64B/66B (e.g., 255/237, 255/238, 66/64) or Any Other Scaling Requirement
• Less than 1ps RMS Output Jitter
• Four Output Clocks in Two Groups
• Nearly Any Frequency from < 1Hz to 750MHz
• Each Group Slaves to a DFS Clock, an APLL Clock, or Any Input Clock (Divided and Scaled)
• Each Has a Differential Output (1 CML, 1 LVDS/ LVPECL) and Separate CMOS/TTL Output
• 32-Bit Frequency Divider Per Output
• Two Sync Pulse Outputs: 8kHz and 2kHz
• General Features
• Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU
• Accepts and Produces Nearly Any Frequency Up to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1,
NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M,156.25M, and Nx19.44M Up to 622.08M
• Internal Compensation for Local Oscillator Frequency Error
• SPI™ Processor Interface
• 1.8V Operation with 3.3V I/O (5V Tolerant)
